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Cadence Design Systems
Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.
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Microwave Office for RF Designers v22.1 Exam
Cadence Design Systems
Xcelium Simulator v24.03 Exam
Cadence Design Systems
Allegro X EDM PCB Librarian vSPB23.1 Exam
Cadence Design Systems
Genus Physical Synthesis Flow v23.1 Exam
Cadence Design Systems
Jasper Scoreboard v1.0 RAKS Exam
Cadence Design Systems
Cadence RTL-to-GDSII Flow v6.0 Exam
Cadence Design Systems
Conformal Low Power Verification with CPF v23.1 Exam
Cadence Design Systems
DE-HDL Library Development using DE-HDL v23.1QIR1 Exam
Cadence Design Systems
Allegro X Design Entry HDL Front-to-Back Flow vSPB23.1 Exam
Cadence Design Systems
Analog Modeling with Verilog-A v23.1 Exam
Cadence Design Systems
Innovus Implementation System (Hierarchical) v23.1 Exam
Cadence Design Systems
C++ Language Fundamentals v24.03 Exam
Cadence Design Systems
Innovus Hierarchical Implementation with Stylus Common UI v23.1 Exam
Cadence Design Systems
Analog Simulation with PSpice using Design Entry HDL vSPB23.1 Exam
Cadence Design Systems
Reliability Analysis in Virtuoso Studio vIC23.1 Exam
Cadence Design Systems
Allegro X System Capture Front-to-Back Flow vSPB23.1 Exam
Cadence Design Systems
Test Synthesis with Genus Stylus Common UI v23.1 Exam
Cadence Design Systems
Cadence and Sumedha IT: Synthesis and Static Timing Analysis - Instructor
Cadence Design Systems
Cadence and Sumedha IT: Languages and Methodologies - Instructor
Cadence Design Systems
Cadence and Sumedha IT: Signoff Timing and Power Analysis - Instructor
Cadence Design Systems
Cadence and Sumedha IT: Simulation, Debug and Coverage - Instructor
Cadence Design Systems
Cadence and Sumedha IT: Digital Physical Design - Instructor
Cadence Design Systems
Cadence and VEDA IIT: Digital Physical Design - Instructor
Cadence Design Systems
Cadence and VEDA IIT: Simulation, Debug and Coverage - Instructor
Cadence Design Systems
Cadence and VEDA IIT: Signoff Timing and Power Analysis - Instructor
Cadence Design Systems
Cadence and VEDA IIT: Languages and Methodologies - Instructor
Cadence Design Systems
Cadence and VEDA IIT: Synthesis and Static Timing Analysis - Instructor
Cadence Design Systems
Low-Power Synthesis Flow with Genus Stylus Common UI v23.1 Exam
Cadence Design Systems
OrCAD X Capture Constraint Manager PCB Flow vSPB23.1 Exam
Cadence Design Systems
support.cadence.com Luminary Winner 2023
Cadence Design Systems
support.cadence.com Luminary Nominee 2023
Cadence Design Systems
Genus Low-Power Synthesis Flow with IEEE 1801 v23.1 Exam
Cadence Design Systems
Advanced SKILL Language Programming vIC23.1 Exam
Cadence Design Systems
Allegro X PCB Editor Advanced Methodologies v23.1QIR1 Exam
Cadence Design Systems
Essential SystemVerilog for UVM v1.2.5rev3 Exam
Cadence Design Systems
Allegro X High-Speed Constraint Management v23.1 Exam
Cadence Design Systems
Allegro X PCB Editor SKILL Programming Language vSPB23.1 Exam
Cadence Design Systems
Advanced Design Verification with the RAVEL Programming Language v23.1QIR1 Exam
Cadence Design Systems
Allegro X PCB Router Basics vSPB23.1 Exam
Cadence Design Systems
ATPG Flow with Modus DFT Software Solution v23.1 Exam
Cadence Design Systems
Innovus Implementation System (Block) v23.1 Exam
Cadence Design Systems
2024 CFD Student Challenge Finalist
Cadence Design Systems
Conformal Equivalence Checking v23.1 Exam
Cadence Design Systems
Analog Simulation With PSpice v23.1 Exam
Cadence Design Systems
Virtuoso Layout Pro: T7 Module Generator and Floorplanner vIC23.1 Exam
Cadence Design Systems
Tempus Signoff Timing Analysis and Closure v23.1 Exam
Cadence Design Systems
Tempus Signoff Timing Analysis and Closure with Stylus Common UI v23.1 Exam
Cadence Design Systems
Innovus Block Implementation with Stylus Common UI v23.1 Exam
Cadence Design Systems
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