ASIC Verification Course- NC State University

Issued by Siemens Software

Earners of this badge are able to verify complex digital designs at block and chip level, identifying the contained bugs, and closing functional coverage, using SystemVerilog. They also can explain the purpose and design of base class packages used in functional verification. Earners also can use a base class package to create layered test benches used in ASIC and FPGA Verification and their implementation using SystemVerilog.

Type Learning
Level Intermediate
Time Months

Skills

Constrained Randomization
Digital Logic
Functional Coverage
Object Oriented Programming Techniques
QuestaSim
Questa Visualizer
System Verilog
UVM Introduction
Verification Process

Earning Criteria

Prerequisite: ECE 564, ASIC and FPGA Design with Verilog, or equivalent.
Instructor approved score on all tests and projects.