SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification v2.0 Exam
Issued by
Cadence Design Systems
The earner of this badge can create accurate high-speed Digital Mixed-Signal (DMS) models by understanding the features and capabilities of System Verilog Real Number Modeling. You will be able to code models for several circuit types and have the foundational knowledge for more sophisticated modeling.
- Type Validation
- Level Intermediate
Skills
Earning Criteria
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Complete the associated course.
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Score 96% or greater on the exam.