Real Number Modeling with SystemVerilog v22.09 Exam
Issued by
Cadence Design Systems
The earner of this badge can create SystemVerilog Real Number Models to enable high-performance digital-centric, mixed-signal SoC verification.
- Type Validation
- Level Intermediate
Skills
- Cadence
- Mixed-signal
- RNM
- SV
Earning Criteria
-
Score 96% or greater on the exam.