Genus Low-Power Synthesis Flow with IEEE 1801 v23.1 Exam
Issued by
Cadence Design Systems
The earner of this badge can use the low-power features of Genus Synthesis Solution to reduce both dynamic and leakage power during synthesis. As well as can use multiple supply voltage (MSV) design, power shutoff (PSO) synthesis, and dynamic voltage frequency scaling (DVFS) synthesis to optimize the design for low-power using IEEE 1801 power intent file.
- Type Validation
- Level Intermediate
Skills
- Cadence
- Genus
- Low-Power
- RTL Synthesis
- Synthesis
Earning Criteria
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Score 96% or greater to pass the exam