Front End Digital Design and Verification Language and Methodology Domain Certification
  • Type Validation
  • Level Intermediate
Additional Details

Front End Digital Design and Verification Language and Methodology Domain Certification

Issued by Cadence Design Systems

The recipient of this badge has completed the certification requirements in languages and methodologies.

  • Type Validation
  • Level Intermediate
Additional Details

Skills

  • Cadence
  • Jasper Formal
  • SystemVerilog
  • UVM
  • Verilog

Earning Criteria

  • The recipient of this badge has completed the following courses and earned badges:
  • 1) Semiconductor 101 v1.0
  • 2) Digital IC design Fundamentals v2.0
  • 3) Verilog Language and Application v28.0
  • 4) SystemVerilog for Design and Verification v21.0
  • 5) SystemVerilog Accelerated Verification with UVM v1.2.6