Designing with Integrity 3D-IC v22.1 Exam
Issued by
Cadence Design Systems
The earner of this badge can create an interposer device, import the ASIC and HBM devices, and perform top-level integration and placement of the devices in Integrity 3D-IC System Planner. They will also be able to perform netlist creation, signal assignement, and bump and TSV creation for the interposer. Lastly, they will also be able to push both the ASIC and interposer designs to Integrity 3D-IC Layout for implementation.
- Type Validation
- Level Intermediate
Skills
- Cadence
- Implementation
- Innovus
Earning Criteria
-
Score 96% or greater to pass the exam