The earner of this badge can create Verilog, Verilog-A, and Verilog-AMS behavioral models to perform functions and verify the functionality and performance of the models . The earner can generate a library of common functions for smoothing discontinuous behavior and model common analog effects and interpolate with table models. The earner can use amsDmv to perform model validation of measured results, waveform signals, pin and module interfaces of a reference and of a compared design.

• Type Validation
• Level Intermediate