Timing Analysis for Altera® FPGAs Course Completion

Issued by Intel

Those with the Altera® Timing Analysis badge have an understanding of the Timing Analyzer timing analysis design flow. They can apply basic and intermediate timing constraints to an FPGA design. They can analyze an FPGA design for timing using the Timing Analyzer. They have acquired knowledge about writing and manipulating SDC files for analysis and controlling the Quartus® Prime software compilation

Additional Details

Skills

Altera FPGA
Analysis
Design Flow
Quartus Design and Debug
Quartus Prime
SDC
synopsys design constraint file
System Verilog
Timing Analyzer
Timing and Optimization
Timing constraints
Verilog
VHDl

Earning Criteria

For this badge, you will complete in entirety the lecture and lab portions of the Timing Analysis class led by an Altera® FPGA Technical Training instructor. This consists of 4 hours of lecture and approximately 4 hours of hands-on lab exercises. The hands-on lab practice will be completed during class time, in a virtual machine environment provided by your instructor.